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MIPI M-PHY Gear3 IP (Silicon Proven in TSMC 28HPC+)
The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear3 rates up to 5.8Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 3 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. The MIPI M-PHY provides robust testability by low cost Build-In-Self-Test (BIST), and receiver eye data monitoring and debugging function for embedded system.
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Block Diagram of the MIPI M-PHY Gear3 IP (Silicon Proven in TSMC 28HPC+)
MPHY IP IP
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- MIPI M-PHY Gear4 IP (Silicon Proven in TSMC 12FFC)
- MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
- MIPI M-PHY G4 Designed For TSMC 28nm HPC+