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MIPI M-PHY GF12/14LPP
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all IOs including primary and secondary ESD.
Features
- Compliant with MIPI M-PHY V0.8
- HS1P, HS1S and LP modes
- Supports DigRF v4 and UniPro MIPI protocols
- Up to 5.0 Gb/s data transfer rate per lane
- TX drivers are programmable for:
- Amplitude
- Slew rate
- De-emphasis
- Auto-calibrated on-die termination
- Spread spectrum clocking (SSC) with:
- Spectrum offset
- Range shape
- Skew rate
- Advanced Rx equalization
- Includes BIST, loop back & boundary scan
- Loop back has 7 different modes
Deliverables
- We can provide the following deliverables to aid quick and reliable integration into the design flow. Please contact us for any additional views:
- GDSII
- Netlist (Spice format for LVS)
- Footprint (LEF format)
- User documentation
- Module integration guidelines
- Datasheet
- Silicon validation report
- Evaluation board
View MIPI M-PHY GF12/14LPP full description to...
- see the entire MIPI M-PHY GF12/14LPP datasheet
- get in contact with MIPI M-PHY GF12/14LPP Supplier