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MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
The silicon-proven DesignWare® MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high-speed interfaces for applications including the JEDEC Universal Flash Storage (UFS), and the MIPI Low Latency Interface (LLI) and UniPro interfaces. By providing an application-oriented M-PHY IP that operates at multiple speeds and is interoperable with multiple protocols, Synopsys enables designers to “future-proof” their designs, while reducing the risk and cost of integrating MIPI interfaces into baseband, application processors and mobile integrated circuits (ICs).
When the DesignWare MIPI M-PHY IP is combined with the DesignWare Universal Flash Storage (UFS) Host Controller IP and DesignWare MIPI UniPro Controller IP, Synopsys provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).
When the DesignWare MIPI M-PHY IP is combined with the DesignWare Universal Flash Storage (UFS) Host Controller IP and DesignWare MIPI UniPro Controller IP, Synopsys provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).
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