MIPI M-PHY - TSMC 40nm
Arasan’s M-PHY’s are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The M-PHY consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
Design Philisophy: Arasan’s approach to M-PHY design is end-to-end protocol specific. Different protocols have different requirements in terms of clocking. A single version of M-PHY that caters to all protocols can become prohibitively large and consume more power than necessary. Hence Arasan delivers the most area and power efficient implementation for each MIPI M-PHY protocol.
Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.
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Block Diagram of the MIPI M-PHY - TSMC 40nm IP Core
mipi m-phy ip core IP
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