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MIPI RFFE Master Controller IP Core
Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial interface which utilizes a bus frequency of up to 26 MHz and timing accurate trigger mechanisms to allow control of timing critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers and Antenna Sensors, which are considered RFFE Slaves.
The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
At a minimum, Arasan delivers RFFE Master in RTL form. Optionally, physical designs of the complete RFFE Master, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request.
The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
At a minimum, Arasan delivers RFFE Master in RTL form. Optionally, physical designs of the complete RFFE Master, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request.
Features
- Compliant with MIPI RFFE Specification 1.10
- Delivered in Reuse Methodology Manual (RMM) compliant Verilog
- RTL format
- Optionally delivered as a physical design
- Small footprint
- Up to 15 Slaves can be connected per RFFE bus
- Low pin count on RFFE interface (SCLK and SDATA)
- Low EMI
- Low power consumption
- Configurable RFFE clock speed of up to 26Mhz
- Half speed read access for slow Slaves
- VIO enable/disable for each slave on RFFE bus
- Supports register 0 write , Register read register write
- AHB Bus support for register configuration using programmed IO
Benefits
- Fully compliant to MIPI RFFE standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Premier direct support from Arasan IP core designers
Deliverables
- IP Deliverables for Digital Core
- Verilog HDL of the IP Core
- User guide
- Gate count estimates available upon request
- Synthesis scripts
- Simulation environment including test bench, BFM’s, and exhaustive test suite
- Additional Deliverables, for Physical Design (optional)
- GDS-II Database
- LVS Netlist
- Physical Abstract Models (LEF)
- Timing Models (LIB)
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