MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI companilitity, it provides a simple interface to a wide range of low-cost devices. The MIPI SPMI Slave IP Core is proven in FPGA enviroment.The host interface of the MIPI SPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
The MIPI SPMI Slave IP Core is supported natively in Verilog, VHDL and SystemC
- Compliant with MIPI STP Specification version 2.0 and 2.2.
- Supports STP interface.
- Supports ATB interface.
- Supports Custom interface.
- Supports a trace stream comprised of 4-bit frames.
- Supports up to 16 independent data Channels per Master.
- Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data.
- Supports Time-stamped data packets using one of several time stamp formats including:
- -> Gray code
- -> Natural binary
- -> Natural binary delta
- -> Export buffer depth (legacy STPv1 timestamp that requires DTC support).
- Supports Data packet markers to indicate packet usage by higher-level protocols.
- Supports Flag packets for marking points of interest (for higher-level protocols) in the stream.
- Supports Packets for aligning time stamps from different clock domains.
- Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC.
- Supports Packets for cross-synchronization events across multiple STP sources.
- Supports for user-defined data packets.
- Facilities for synchronizing the trace stream on bit and message boundaries.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The MIPI SPMI Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User s Guide and Release notes.