Fully Digital Physically Unclonable Function (PUF) - PQC Ready
This includes the follow features:
• Separate versions for CSI-2 Transmit, CSI-2 Receive, DSI Host (Transmit), DSI Peripheral (Receive)
• Logging and display of all MIPI traffic in a user-friendly format
• Provided with an extensive set test scripts
The fast setup and operation of the MIPI Testbench makes it easy for users to quickly and comprehensively perform end-toend simulations of their MIPI design.
The Testbench is fully compliant with CSI and DSI specifications.
The MIPI Testbench is not a full MIPI compliance suite. Contact Rambus for its recommended third-party MIPI Compliance Suite for ASIC validation.
Rambus also provides IP Core customization services.
Contact Rambus for a quote.
View MIPI Testbench full description to...
- see the entire MIPI Testbench datasheet
- get in contact with MIPI Testbench Supplier
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 Controller Core
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave