The UFS is a simple, high performance, serial interface used in mobile systems as a mechanism to communicate between host processor and mass storage devices like Flash and other non-volatile memories. This communication is achieved using a UFS Host and UFS Device, using MIPI UniPro and MPHY as Link and PHY layers respectively. UFS Device UTP Layer does the function of encoding and decoding UPIUs and forwarding of SCSI commands to the SCSI command decoder.
The UFS Host & Device works perfectly with our MIPI UniPro and GDA Partner's MPHY. With this, we provide the complete solution including software.
UTP Device, DMA registers are programmed by software using AHB slave interface.AXI Master Interface is used by the DMA engine to send the data of the dataout UPIU and to receive the data for datain UPIU. AXI Master Interface is also used by DMA engine to fetch the query descriptors from the device server. UTP engine controls the UPIU encoding and decoding and for detecting and reporting errors. UniPro interface controls the data transfer through CPORT. MIPI UFS’s UTP layer forwards the command , query , task management UPIU’s relevant fields to the Device server for further processing.
- Complaint with UFS 1.0 spec, UFS Host Controller Interface V1.0, MIPI UniPro V1.41, MIPI M-PHY spec v2.0.
- • Lanes of each sub link (TX and RX) can be programmed separately up to 4lanes.
- • M-PHY PWM and HS data rates HS1X, HS2X supported.[3Gbps-6Gbps per lane in HS mode]
- • Supports configurable outstanding commands/Query request UPIU for UTP layer in UFS device.
- • Decoding and Encoding of all the UPIU’s required for UFS
- device supported.
- • Configurable LUN(Upto 8).
- • Error Reporting and Handling supported.
- • AXI3 and AHB used for easy integration into SOC.
- Highly modular design
- Fully synchronous design
- Configurable IP
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
Block Diagram of the MIPI UFS Device IP Core