MIPI UNIPRO compatible with MIPI UNIPRO version 1.8 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI UNIPRO IIP is proven in FPGA environment. The host interface of the MIPI UNIPRO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon,PLB, Tilelink, Wishbone or Custom protocol.
- Implemented in Unencrypted Verilog, VHDL and SystemC
- Supports NAND Flash memory devices from all leading vendors.
- Supports 100% of NAND FLASH protocol standard of HY27UH08AG(5/D)M.
- Supports all the NAND FLASH commands as per the specs.
- Provides cost effective solutions for mass storage applications.
- Supports NAND interface of x8 width.
- Supports multiplexed Address/Data.
- Supports memory cell array of (2K+64) Bytes *64 Pages*16,384 Blocks.
- Supports page size of (2K + 64 spare) Bytes for x8 device.
- Supports Block size of (128K + 4K spare) Bytes for x8 device.
- Supports page read/program.
- Supports Copy back program mode for fast page copy without external buffering.
- Supports cache program mode to improve the program throughput.
- Supports Fast block erase time of 2ms.
- Supports status register.
- Supports Electronic signature.
- Supports Chip enable don’t care.
- Supports Hardware data protection.
- Supports Data integrity of 100,000program/erase cycles.
- Implemented in Unencrypted OpenVera, Verilog, SystemC and SystemVerilog.
- Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
- Fully synthesizable
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The MIPI UNIPRO interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis and Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.