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MIPI Universal D-PHY in UMC 40nm LP
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low powerfunctions are mostly used for control.
The IP can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low powerfunctions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports the MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializers and Deserializers included
- Low power dissipation
- Loopback testability support
- Optional resistance termination calibrator
Deliverables
- Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- RTL
- One year support
Applications
- Mobile
- Automotive
- IoT
- Consumer Electronics
- VR
- AR
Block Diagram of the MIPI Universal D-PHY in UMC 40nm LP
Video Demo of the MIPI Universal D-PHY in UMC 40nm LP
We demonstrate our customer demo, the Lattice Crosslink FPGA Video Bridge, featuring Mixel's MIPI D-PHY Universal IP.
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- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
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