Imagination's interAptiv family is the latest generation of the MIPS family multi-threaded (MT), multi-core, 32-bit processors from MIPS. The use of MT, improvements to multi-core performance, and additional core enhancements for error correction and power management, make interAptiv among the most performance-efficient and feature-rich CPU core in its class.
With the interAptiv core, designers have access to two virtual processing elements (VPEs), or hardware threads, which appear as two complete processors to an SMP operating system. These threads efficiently use a shared execution pipeline resulting in very high efficiency in terms of area and power relative to competing cores in the same class, as measured by the industry-standard CoreMark™ benchmark. Threads can also be managed using the hardware scheduler and inter-thread communication features. High efficiency and access to thread-level management make the interAptiv core the ideal solution for applications that are highly threaded and require support for Quality of Service (QoS).
Next-generation SoCs are increasingly moving towards multi-core designs even in mid-range markets such as the entry-level smart phone market. The interAptiv core utilizes our latest multi-core interconnect, the 2nd generation Coherence Manager (CM2), which has an integrated L2 cache. The CM2 improves multi-core performance by simultaneously reducing latency and increasing bandwidth. The CM2 supports up to four interAptiv CPUs or eight virtual processors in a single, fully coherent, multi-processor system.