Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
Mobile Phase Recovering Equalizer FPGA core
The Mobile Phase Recovering Equalizer fits easily into the signal flow of most single-carrier demodulators with a minimal amount of configuration and supporting input signals.
View Mobile Phase Recovering Equalizer full description to...
- see the entire Mobile Phase Recovering Equalizer datasheet
- get in contact with Mobile Phase Recovering Equalizer Supplier
Block Diagram of the Mobile Phase Recovering Equalizer FPGA core

Phase Recovering Equalizer IP
- LMS Adaptive Channel Equalizer
- 32G Multi-protocol SerDes PHY
- USB 3.0 Gen1 / Gen2 Host Controller IP
- Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process