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Mobile Single Data Rate SDRAM Controller
The SDR-SDRAM-CTRL core provides a simplified, pipelined and burst-optimized interface to all industry-standard Mobile and ordinary SDRAM devices currently on the market.
Features
- Interfaces directly to Mobile and ordinary SDR (Single data rate) devices
- Supports all standard SDRAM chips and registered/unbuffered DIMMs
- Pipelined design achieves maximal memory-bandwidth utilization
- Bank status monitoring
- Supports up to 2G address space
- Supports 1 to 8 chip-selects, 2 to 4 banks, 11 to 14 row bits and 8 to 12 columns bits
- Runtime-configurable timing parameters (CAS latency, tRP, tRCD, tREFC, tMRD, etc.)
- Runtime-configurable memory settings (Row bits, Column bits, Bank bits, number of CSs)
- Runtime configurable Mobile-SDR support and Extended-Mode-Register (EMR) values
- Configurable auto-close mechanism
- Low-power support. Can automatically enter into power-down or selfrefresh mode
- Programmable automatic refresh policy
- Flexible user-interface
- Three independent paths (control, write-data and read data) for maximum performance
- Integrated read and write-data FIFOs
- Supports any arbitrary length burst access (1 to 216)
- Can be easily interfaced to high performance on-chip synchronous microprocessor busses that support pipelining and burst-accesses or to on-chip FIFOs. Respective wrappers are available on request.
- Optional AHB bus interface
- Efficient architecture easily fits into Actel FPGAs:
- Uses 2,479 of 6,144 Tiles (40%) of an Actel A3P250 ProASIC3 Device with -2 speed grade for 77 MHz operation
- Uses 2,479 of 6,144 Tiles (40%) of an Actel AFS250 Fusion Device with -2 speed grade for 72 MHz operation
View Mobile Single Data Rate SDRAM Controller full description to...
- see the entire Mobile Single Data Rate SDRAM Controller datasheet
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