The CEVA-BX2 audio/voice DSP is targeted for high performance audio devices such as DTV, Smart Speaker, Soundbar, and car infotainment systems.
CEVA-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16×8-bit and 8×8-bit MAC operations.
The CEVA-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node.
The CEVA-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.
The CEVA-BX2 is accompanied by a comprehensive software development tool chain, including:
* Advanced LLVM compiler
* Eclipse based debugger
* DSP and neural network compute libraries
* Neural network frameworks support
* Real Time Operating Systems (RTOS)