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MPEG-2 HD Decoder - Supports 1080p60. 4:2:2. 8-bit,
The MPEG-2 Decoder Core is a high performance and high quality solution video decompression engine targeted primarily at FPGAs. It is compliant with ISO/IEC 13818-2 (H.262) standards. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial
bus with embedded sync information. The decoder requires single external DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
bus with embedded sync information. The decoder requires single external DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
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Block Diagram of the MPEG-2 HD Decoder - Supports 1080p60. 4:2:2. 8-bit,
MPEG-2 HD Decoder IP
- CODA7L - H.264 HP, VC-1 AP, MPEG-4 ASP, MPEG-2 MP, VP8, AVS up to 1080p 30fps for decoder and H.264 BP, MPEG-4 SP, H.263 P3 up to 1080p for encoder
- H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0
- CODA988 - H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps