PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
MPEG-2 HD Decoder - Supports 1080p60. 4:2:2. 8-bit,
bus with embedded sync information. The decoder requires single external DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
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Block Diagram of the MPEG-2 HD Decoder - Supports 1080p60. 4:2:2. 8-bit,

MPEG-2 HD Decoder IP
- CODA7L - H.264 HP, VC-1 AP, MPEG-4 ASP, MPEG-2 MP, VP8, AVS up to 1080p 30fps for decoder and H.264 BP, MPEG-4 SP, H.263 P3 up to 1080p for encoder
- H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0
- CODA988 - H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps