The Trilinear Technologies M2 digital video decoder core is designed specifically for applications that demand high performance with uncompromising video quality. The fully synchronous M2 core is capable of decoding Main Profile @ High Level bit streams using a high speed direct to memory interface. The High Level is supported for the decoding of all profiles which include the 720p, 1080i, and 1080p formats with frame rates up to 120 Hz and compressed bit rates up to 125Mbits per second.
Compressed video streams are received through a flow control managed interface for maximum performance. Host system communication utilizes an industry standard AMBA APB or AHB slave interface. In most applications, the M2 core implements an autonomous decoding mode where operation proceeds without intervention from the host until a specified break point is reached. Control and status information provides real-time visibility for applications requiring fine control of the decode process.
An external frame store is accessed through a direct high speed, wide bus, memory interface designed for compatibility with most external DDR controllers. Decoded picture storage can be configured based on the input video stream which allows the minimum amount of memory to be allocated for a specific decode profile. The memory system is tolerant of high latency which is ideal for implementation in a shared memory system.
The M2 Digital Video Decoder core ships with a fully documented reference driver and a sample video player application. The core is available for demonstration on the Trilinear Technologies’ Viper Development platform. This FPGA based reference system provides a complete environment for core evaluation as well as early software development.
The M2 core can be delivered as either a technology specific firm core or a technology independent soft core and may be implemented on both FPGA and ASIC platforms. The Trilinear Technologies’ development process allows for the migration of soft cores from FPGA to ASIC for prototyping and production solutions with no core modifications.
- Decodes up to Main Profile at High Level
- IEEE-1180 Compliant IDCT Engine
- Supports 4:2:2 and 4:2:0
- Capable of decoding a single HD stream or multiple SD streams
- Supports full performance FPGA and ASIC Implementations
- Main Profile Support
- I, P, B-frames
- Interlaced Coding
- High Level Profile Support
- Supports 1080p60 decode
- 4:2:2 Color Space
- 8, 9, 10 and 11 bit IntraDC precision
- Core Details
- Low CPU Overhead
- Designed for a Shared Memory
- Multi-stream capable
- Low core clock rate
- Up to 120Mb/sec @ 150MHz
- FPGA Development Platform
- 32-bit MIPS CPU based system
- DVI Video Output
- Downloadable Application Software
- CompactFlash Stream Storage
- Hardware Driver and Reference Player Included
- HDL source files for the function design
- HDL source files for block level and top level testing
- Functional specification
- Timing constraints summary document
- C Reference Driver and Player Application
Block Diagram of the MPEG-2 ML@HL Digital Video Decoder