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MPEG -2 Transport Stream Decoder
The Trilinear Technologies M107 Transport Stream Decoder offers ISO13818-1 compliant transport stream decoding with performance and flexibility for a broad range of applications. With powerful packet ID and section filtering capabilities, the M107 processes serial or parallel bit streams at up to 150Mbits per second. The core is available with either an industry standard AMBA 2.0 High Speed Bus interface or an ABMA 3.0 AXI interface. Delivered as a flexible soft core, the M107 is available for ASIC and FPGA implementations using the same code base without the need for hand-crafted adaptation.
Worldwide data decryption is supported using optional modules for each standard. The M107 Decoder supports the TDES, DVB, AES, and Multi2 standards. Each of these standards may be optionally included in the core as required for the application.
The M107 TSD core ships with a complete ‘C’ reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Vantage Development platform based on the Xilinx Virtex5 FPGA family. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
Worldwide data decryption is supported using optional modules for each standard. The M107 Decoder supports the TDES, DVB, AES, and Multi2 standards. Each of these standards may be optionally included in the core as required for the application.
The M107 TSD core ships with a complete ‘C’ reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Vantage Development platform based on the Xilinx Virtex5 FPGA family. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
Features
- Overview
- ISO 13818-1 Compliant
- Supports DVB, ATSC, ARIB,OpenCable
- Integrated decryption support
- Supports FPGA and ASIC Implementations
- Decode Details
- 32 PID Filters
- 32 section filters with 12 byte filter length
- 1-bit serial or 8-bit parallel input interface
- AMBA AHB or AXI
- System clock management
- Integrated Decryption
- TDES with ECB, CBC, and CTS
- AES with ECB, OFB, CTR, CBC, and CFB
- DVB-CSA
- Multi2 with ECB, OFB, CBC, and CFB
- Reference Software
- Complete reference driver
- Stream parser sample application
- C source code provided
- FPGA Development Platform
- 32-bit MIPS CPU based system
- DVI Video Output
- Downloadable Applications
- CompactFlash Stream Storage
- Hardware Driver and Reference Player Included
Deliverables
- HDL source files for the function design
- HDL source files for block level and top level testing
- Functional specification
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
- C Stream Parser Application
Block Diagram of the MPEG -2 Transport Stream Decoder IP Core
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MPEG -2 Decoder IP
- H.264, MVC, VP8, MPEG-1/2/4, VC-1(WMV), RV(RMVB), AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0
- CODA7L - H.264 HP, VC-1 AP, MPEG-4 ASP, MPEG-2 MP, RV8/9/10, VP8, AVS up to 1080p 30fps for decoder and H.264 BP, MPEG-4 SP, H.263 P3 up to 1080p for encoder
- MPEG-2 decoder for high-performance applications (up to multi-channel DCI 2K and 4K, HD 1080i and 1080p)
- MPEG-1/2 – Layer I/II Audio Decoder
- MPEG-1/2 + AAC Audio Decoder
- MPEG-2 ML@HL Digital Video Decoder