Multi-channel HDTV 1080p@30/1080i@60 H.264/AVC Encoder

Features

• Encoder fully compatible with the ITU-T H.264 specification.
• Decoder limited to the subset produced by the encoder
• Encoder proven in FPGA : VGA (640x480) at 30 fps or 720p @ 15 fps in Virtex4-10 demo board with video streamed to Ethernet.
• Profile level 4.1, can be decoded by Baseline, Main or Hi Profile decoder.
• Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive or 60 fields/s interlaced).
• Direct support of both progressive and interlaced video.
• Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps or 1920x1080 @ 60 fields/s.
• Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end FPGAs (Virtex4-5/StratixII-III) .
• 4 CIF (704x576) at 30 fps in low end FPGAs (Spartan3-4, slowest speed grade).
• Encoder and decoder support up to 32 video channels simultaneously.
• No CPU required for encoding.
• Variable Bit Rate (VBR) and Constant Bit Rate (CBR).
• Very low latency (~1.1 ms for VGA @ 30 fps).
• Motion vector up to –16.00/+15.75 pixels around the predicted motion vector (-24.00/+23.75 around the origin), down to quarter pixel. Decoder up to –32.00/+31.75, quarter pixel.
• Support for most of intra4x4 and all intra16x16 modes.
• Multiple slices support for better error resilience.
• Block skipping logic for lower bitrate.
• Deblocking filter for better quality.
• External memory interface tolerant of high latencies and delays, ideal in a SoC system or in a shared bus with a CPU. The memory interface can be clocked at a different frequency from the core for easier integration.
• Supports YUV 4:2:0 video input
• Min Clock speed = 4 x the raw pixel clock speed
• Low gate count encoder (from 145K gates + 133 Kbits of RAM for real time VGA encoding to 195 Kgates + 133 Kbits of RAM for real time 1080p encoding).
• Low gate count decoder (up to 70 Kgates+ 75 Kbits of RAM for real time 1080p decoding).
• Simple, fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.

Deliverables

• Available as fully functional and synthesizable VHDL or Verilog soft-core
• C model of the IP is available now for evaluation.

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