The increased availability of high performance SerDes technologies offers integrated solutions for flexible multiport devices that can dynamically adapt to available channel capacity.
MorethanIP's Hydra-Family of Multi-Channel Multi-Rate Ethernet MAC/PCS Cores provide unique and flexible solutions for applications requiring configurable dynamic rates for a varying set of serial links.
The Cores implement the complete MAC and PCS layers and optionally PMA layer functions for Backplane Autonegotiation and Link Training covering a broad range of applications. Depending on the available SerDes channels either a combined full rate 40G link can be established, or the individual channels can operate as independent 100M/1G/2.5G/10G links.
On the Line side, the Core implements flexible parallel serdes interfaces easing integration with any SerDes technology.
The application interface can be chosen to implement individual FIFO interfaces or use a time multiplex function to interface with the individual channels.
With its advanced rate adapting design the MorethanIP MAC and PCS Cores allow for very efficient and low latency implementations avoiding rate-matching FIFOs between the MAC and PHY Layers.
The core is delivered either in generic Verilog synthesizable HDL for ASIC and FPGA implementations, or in an encrypted format for FPGA implementations. MorethanIP offers customized variations of this solution targeting customer needs with specific rate and channel requirements.