The increased availability of high performance SerDes technologies offers integrated solutions for flexible multiport devices that can dynamically adapt to available channel capacity.
MorethanIP's Hydra-Family of Multi-Channel Multi-Rate Ethernet MAC/PCS Cores provide unique and flexible solutions for applications requiring configurable dynamic rates for a varying set of serial links.
The Cores implement the complete MAC and PCS layers and optionally PMA layer functions for Backplane Autonegotiation and Link Training covering a broad range of applications. Depending on the available SerDes channels either a combined full rate 40G link can be established, or the individual channels can operate as independent 100M/1G/2.5G/10G links.
On the Line side, the Core implements flexible parallel serdes interfaces easing integration with any SerDes technology.
The application interface can be chosen to implement individual FIFO interfaces or use a time multiplex function to interface with the individual channels.
With its advanced rate adapting design the MorethanIP MAC and PCS Cores allow for very efficient and low latency implementations avoiding rate-matching FIFOs between the MAC and PHY Layers.
The core is delivered either in generic Verilog synthesizable HDL for ASIC and FPGA implementations, or in an encrypted format for FPGA implementations. MorethanIP offers customized variations of this solution targeting customer needs with specific rate and channel requirements.
- MAC , RS and PCS implementation compliant with IEEE802.3 specifications
- 4 Line interfaces offering flexible rate support for standard 10/100/1000 SGMII, or industry standard 2.5G , or 10G Base - R operation independently per SerDes link .
- Dynamically configurable to operate as 4 individual 1G/10G channels , each with independent rates, or as a full capacity 40G channel with 40G Base - R PCS Optional integration of Clause 72 Link Training functions for Base - KR Backplane applications
- Optional integration of Clause 73 Backplane Autonegotiation function per serdes lane
- Optional integration of Clause 74 Forward Error Correction (FEC) for Base - KR backplane applications
- Full - duplex line rate support at all speeds
- Standard preamble / SFD (Start of Frame Delimiter) insertion and deletion with optional custom preamble
- Lane, data alignment, PHY error and local/remote fault signaling handled by the Core's Reconciliation sub - layer
- Optional MAC address match on receive and overwrite on transmit with programmable promiscuous mode operation
- Optional Multicast address filtering with 64 - bin hash code lookup on receive reducing load on higher layers
- Ethernet Pause Frame (802.3 Annex 31 B ) generation and termination for automatic a s well application controlled flow control
- Support for Priority Flow Control (PFC , 802. 1 Qbb ) frames allowing control for 8 classes for congestion management individual per channel .
- Programmable frame maximum length up to 32K byte
- Support for 802.1Q VLAN tagged frames
- Dynamic inter packet gap (IPG) calculation for LAN/WAN applications with Deficit Idle Counter (DIC) for optimized performance with minimum IPG
- Clock and data rate decoupling with programmable asynchronous FIFOs at the application interface
- Statistics 64 - Bit counters for IEEE 802.3 basic and mandatory Management Information Database (MIB) package as well as Ethernet MIB (RFC 2665) and Remote Network Monitoring (RFC 2819)
- TX/RX Timestamping enabling IEEE 1588 applications
- Support for Energy Efficient Ethernet (EEE) 802.3az
- Integrated MDIO Master supporting both Clause 22 and Clause 45 managed PHY modules
Block Diagram of the Multi-Channel/Multi-Rate Quad 1G/10G/40G Ethernet MAC/PCS Core