Multi-Gigabit/s serial transceivers are fast replacing older parallel interfaces in most of applications. The accelerating demand for higher data rates and serial I/O density poses challenging performance requirements for next generation SerDes designs due to area and power budget limitations. High-speed transceivers must handle multiple data rates to accommodate new link speeds and standards, yet retain backwards compatibility for legacy systems. At higher rates, the various blocks must satisfy stringent performance specifications to meet the requirements of the overall link design, especially with respect to the jitter budget. By the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO design has evolved to include more complex schemes and techniques.
With sophisticated architecture and advanced technology, HES multi-mode transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the programmable logic resources of the FPGA, it can support a wide variety of serial data transmission protocols with link rate from 300Mbps to 10.3125Gbps.
- 1. 4 Channel per Quad, X4~X12 Quads, 300Mbps~10.3125Gbps
- 2. Low Power Consumption (PCS+PMA)
- With sophisticated architecture and advanced technology, this SerDes IP has configurable flexibility to support tens of industry protocols, such as PCI-E, SATA/SAS, Ethernet, CPRI, RapidIO, XAUI etc. High performance adaptive DFE with 4 taps for long reach application and low power mode adaptive CTLE for short reach are integrated. the rms jitter of high speed clock can achieved less than firstname.lastname@example.orgGHz with inductor-less Oscillator.
- 2.Characterization Report
- 3.Flat Netlist (cdl)
- 4.Layout View (gds2)
- 5.Abstract View (lef)
- 6.Timing View (tlf)
- 7.Behavioral Model (VHDL/Verilog)
- 8.Integration Support