"The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe Ethernet.
It brings a high performance, low latency, safe and cyber-secure link between your software application and the ARINC664p7/Ethernet network.
The CetraC technology is fully compliant with ARINC664 Part 7 and Ethernet standards. It allows both cyclic and event-driven communications in full duplex. A 100% hardware solution with embedded ARINC664 Part 7 redundancy management feature to free more power to your CPU.
It uses a PCI, PCI Express or AXI backend interface to connect to a large portfolio of processors within a very short Time To Market.
By using our CetraC technology you get a safe and cyber secure link from your end user software application up to the network with the smaller footprint in the market.
The IEEE1588 PTPV2 protocol is also available at any port to synchronize the overall devices connected to the network. The CetraC EndSystem IP core acts as GrandMaster or simply distributes the clock to each connected equipment requiring a common clock.
Several IP core switches can be connected together through a 10Gbps optical fiber link to create any of the three kinds of flexible network architectures for critical systems:
• High speed redundant ring architecture (at up to 10Gbps)
• High speed hierarchical architecture (at up to 10Gbps)
• Mesh network by mixing the two previous architectures."
- "Ethernet/TSN/ARINC664P7 EndSystem with customizable number of ports up to 1 Gbps.
- Support IEEE 1588 PTPV2 as GrandMaster or User
- Safe & Secure Ethernet communication
- Modularity and Scalability capabilities by implementing easily up to 24 ports
- Master Clock Synchronization
- Compliant with ARINC664 Part 7 (AFDX)
- Compliant with ARINC664 Part 7 at 1Gbps (Safe Ethernet)
- Compliant with IEEE802.3; UDP, TCP, ICMP, ARP
- Compliant with IEEE-1588
- DO-254 Certification Kit up to DAL-A"
- It supports in one core multi Ethernet based protocols as ARINC664p7, IEEE802.3, IEEE1588 for the smallest footprint available
- 100% Hardware implementation to target both ASIC and FPGA device :
- Manage Deterministic and best effort frames without compromise
- Cyber Security friendly
- Highly modular and scalable to match easily new protocol standard
- "Encrypted RTL source code compliant with CetraC design standard
- Reference Design as integration example
- Configuration Software tools and Library for Linux-RT Operating System: Linux, Windows, VxWorks.
- Support includes technical integration, DO-254 integration"
- Also available as COTS hardware in our switch named Babelya for prototyping and evaluation purposes
- used as central element of your safe and cyber-secure network
Block Diagram of the Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
Video Demo of the Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
CetraC Video Channel