EXTOLL's SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and also reduces the effort for migration to alternate target technologies.
A single SerDes PHY block can consist of up to 8 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 2.5 to 25 Gbps. Multiple PHY blocks can be combined to construct wider links such as 16x PCIe. Higher line rates up to 28 Gbps can be supported on request.
- Support for line rates in the range of 2.5 up to 25 Gbps
- Compliant with PCIe up to Gen3, Gen4 validation to follow
- 10G Ethernet (10GSFP+Cu defined in SFF-8431)
- Programmable transmitter with equalizer (4 tap FIR)
- Programmable RX linear equalizer (CTLE)
- Programmable RX DFE (5 tap)
- Digital high speed PLL (low jitter)
- Pattern Generator (PRBS, user defined pattern)
- Concurrent Eye Monitor for equalization and channel analysis
- Far End and Near End Loopbacks
- Protocols: Ethernet , Hybrid Memory Cube Memory Model (HMC), PCIe, RapidIO
- Size: 320 um x 855 um
- Frontend Views
- Backend Views