Multi-Standard DVB-T2/C2/S2 Decoder IP Core

Features

• All DVB-T2, DVB-C2 and DVB-S2 modes
• Compliant to ETSI EN 302 755, ETSI EN 302 769, ETSI EN 302 307
• Dedicated DVB-T2, -C2 and -S2 Pre-Processing with Resource Sharing
• All Deinterleaving steps (frequency, time, cell,...)
• Optimized high performance FEC engine
• Single LDPC/BCH Decoder shared for all modes
• FEC engine parameters optimized for target throughput / application
• DVB-T2 Data-PLP, Common-PLP, L1-pre & L1-post Decoding
• DVB-C2 Data-PLP, Common-PLP, L1 Header & L1 part2 Decoding
• DVB-S2 Dual channel & PLH Decoding
• Output Processing
• TS / GSE / GFPS / GCS output
• De-Jitter Buffering and PLP Re-combination into single output stream
• Standard AHB Interfaces for Host control and Memory Access
• Timing-critical tightly-coupled memories embedded in IP
• Large non-timing-critical memories external to IP
• Optimized compile options targeted for ASIC and FPGA applications

Block Diagram of the Multi-Standard DVB-T2/C2/S2 Decoder IP Core

• see the entire Multi-Standard DVB-T2/C2/S2 Decoder datasheet
• get in contact with Multi-Standard DVB-T2/C2/S2 Decoder Supplier