This 12.5Gbps SERDES IP is designed for smooth integration of Multiple SERDES lanes offering best in class performance, area and power. The programmable PHY supports major standards such as PCIe Gen 1/2/3, USB 3.0 / 3.1, XAUI, SATA Gen 1/2/3, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.
- Single SERDES Design that meets wide range of Standards, Protocols and Speeds.
- Any combination is possible, e.g. USB-3.0, PCIe Gen-3 and SATA Gen-3 in a single Combo SERDES.
- Internal Low Jitter PLL support the various standards clocking requirements- no need for additional components.
- Flexible Design- Tile Based Design that enable customer to select any number of Tx and Rx Lanes.
- One Time Effort in design, integration, verification and silicon validation.
- Save Chip area as it there is no need to duplicate logic when few standards are required.
- Future Proof Design- design today with your interface roadmap already embedded and verified.
- Silicon Proven on several Foundries and Process technologies.
- Unequal number of transmit and receive lanes supported
- Data rate programmable 1.25-12.5 Gbps
- Transmit Driver with programmable output swing 100 – 1100 mVp2p
- Pre/Post cursor Transmit equalization range 0 – 9db/12db with 20mV programmability step
- Adaptive Receiver equalization (CTLE + DFE) to support long-reach channel with insertion loss of 30db at 6GHz
- Embedded low jitter phase-locked-loop (PLL)
- Beacon, Low-Frequency-Periodic-Signaling (LFPS), Auto-negotiation (AN) Signaling supported
- Rich in DFT features (AC-JTAG, Eye-scan, Loop-back, RX Sensitivity BIST, TX level BIST, PLL BIST)
- Stuck-at & TFT scan for digital
- Boundary scan (Extest) for integration with SOC scan compressor
- Tests can be done on low cost digital tester
- User’s Manual
- Package/PCB guideline
- SDK (standard design kit) including verilog model, .lib/.db file, .lef file