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Multi State Viterbi Decoder IP Core
The Multi State Viterbi Decoder IP Core is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed for maximum flexibility, allowing it to decode various communications standards, as well as custom coding solutions.
Features
- 16, 32, 64 or 256 states (constraint length 5, 6, 7 or 9) Viterbi decoder
- Up to 398 MHz internal clock
- Up to 39.8 Mbit/s for 16, 32 or 64 states or 11.7 Mbit/s with 256 states
- Rate 1/2, 1/3, or 1/4 (inputs can be punctured for higher rates)
- 6-bit received signed magnitude data
- Optional block decoding with or without tail
- Estimated channel bit error outputs
- Optional serial or parallel data input
- Optional automatic synchronisation for rate 1/2 QPSK and rate 1/2 to 1/4 BPSK
- Free simulation software
- 1073 6-input LUTs. 1, 2 or 4 18KB BlockRAMs.
- Asynchronous logic free design
- Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.
Deliverables
- All Licenses
- Xilinx VHDL Core
- Test vector generator
- ASIC License
- VHDL ASIC Core
- C++ bit/cycle exact simulation model
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