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Multiplying Delay-Locked Loop - TSMC 90 nm
The Multiplying delay-locked loop (MDLL) clock multiplier accept an input clock and generates a phase-locked output clock at a multiple of the input clock frequency. As with a DLL, each rising edge of the input clock zeros the phase error of the loop. Hence this circuit combines the low phase noise of a DLL with the clock multiplication ability of a PLL. A divide-by-M counter provides a programmable multiplication ratio for the MDLL.
Features
- TSMC 90 nm CMOS
- Low jitter
- Precisely aligns the clock distribution output with a reference clock
- Low current consumption
- Compact implementation of the lowpass filter
- Supported foundries: TSMC, UMC, Global Foundries, SMIC
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Applications
- Frequency synthesizer
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Multiplying delay-locked loop MDLL IP
- Delay Locked Loop IP
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm GC (CLN80GC)
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm G (CLN90G)
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm GT (CLN90GT)
- Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT)
- Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm LP (CLN90LP)