90nm OTP Non Volatile Memory for Standard CMOS Logic Process
Multipurpose Hybrid DSP and Controller Architecture Family
As designers are required to efficiently build ever-more complex applications that balance signal processing and control workloads, a new breed of DSP architecture that combines the inherent low power requirements of DSP kernels with high-level programming and compact code size requirements of a large control code base, is required.
The Ceva-BX architecture delivers excellent all-round performance for a new generation of smart devices by providing the perfect alternative for special purpose DSPs and MCUs with DSP co-processors that cannot handle the diverse algorithm needs of today’s applications.
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Block Diagram of the Multipurpose Hybrid DSP and Controller Architecture Family
DSP IP
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