From consumer to industrial, from automotive to healthcare – new algorithms blend digital signal processing and digital signal control for fusing multiple sensors, for interpreting data at the edge, and for connecting to the cloud using multimode wireless connectivity.
As designers are required to efficiently build ever-more complex applications that balance signal processing and control workloads, a new breed of DSP architecture that combines the inherent low power requirements of DSP kernels with high-level programming and compact code size requirements of a large control code base, is required.
The CEVA-BX architecture delivers excellent all-round performance for a new generation of smart devices by providing the perfect alternative for special purpose DSPs and MCUs with DSP co-processors that cannot handle the diverse algorithm needs of today’s applications.
- Parallel processing SIMD Instruction Set Architecture
- 5-way VLIW micro-architecture
- Single or dual scalar compute engines
- 11-stage pipeline
- Speed of 2 GHz at TSMC 7nm process
- Up to 4.5 CoreMark/MHz score
- Support for neural network edge inference
- Half, single and double precision IEEE floating point units
- Trusted execution modes for high security provisioning
- Fully cached memory subsystem
- Automatic Queue and Buffer management mechanisms to integrate co-processors and create a cluster of CEVA-BX cores
- - Comprehensive software development tool chain, including an advanced LLVM compiler, Eclipse based debugger, DSP and neural network compute libraries, common neural network frameworks support, and choice of industry leading Real Time Operating Systems (RTOS).
- Wireless terminals
- Wireless basestations
- IoT and cellular M2M
- Wireless modems
- Home networking
Block Diagram of the Multipurpose Hybrid DSP and Controller Architecture Family