The Xelic Multi-Rate ATM Processor Core (XCA12M) contains independent Transmit and Receive Processor modules for STS-3/STM-1 or STS-12/STM4 SONET/SDH frame data rate applications. Incoming/outgoing data is transferred with an input clock rate up to 100Mb/s using an 8-bit data bus.
The XCA12M Transmit Processor interprets incoming ATM cells and performs rate adaptation through the insertion of configurable IDLE cells. Incoming system side ATM cells are processed with invalid cell detection. Header Error Control field information is optionally calculated and inserted into transmitted cells with COSET addition available through input signal conditioning. Diagnostics support includes optional corruption of inserted HEC and scrambling enable/disable capability.
The XCA12M Receive Processor performs cell delineation and generates Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD) status signals. Interpreters are implemented to detect idle cell, corrupted cell, and valid cell conditions. Single header bit errors are optionally corrected and multiple error headers are detected and dropped. Status signaling is provided for idle cell detection, corrected cells and uncorrected cells. A system side FIFO interface includes signaling for Start of Cell (SOC), End of Cell (EOC) and data valid.