The Xelic Multi-Rate ATM Processor Core (XCA12M) contains independent Transmit and Receive Processor modules for STS-3/STM-1 or STS-12/STM4 SONET/SDH frame data rate applications. Incoming/outgoing data is transferred with an input clock rate up to 100Mb/s using an 8-bit data bus.
The XCA12M Transmit Processor interprets incoming ATM cells and performs rate adaptation through the insertion of configurable IDLE cells. Incoming system side ATM cells are processed with invalid cell detection. Header Error Control field information is optionally calculated and inserted into transmitted cells with COSET addition available through input signal conditioning. Diagnostics support includes optional corruption of inserted HEC and scrambling enable/disable capability.
The XCA12M Receive Processor performs cell delineation and generates Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD) status signals. Interpreters are implemented to detect idle cell, corrupted cell, and valid cell conditions. Single header bit errors are optionally corrected and multiple error headers are detected and dropped. Status signaling is provided for idle cell detection, corrected cells and uncorrected cells. A system side FIFO interface includes signaling for Start of Cell (SOC), End of Cell (EOC) and data valid.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCA12M core available under flexible single use licensing terms with netlist or source code deliverables.
- Compliant with ITU I.432.1 and ITU I.432.2 Specifications.
- Provides full duplex operation with independent transmit and receive functionality.
- Optional self synchronous scrambler/descrambler operation.
- Optionally calculates and inserts HEC (COSET addition available through input signal conditioning) with corruption capability for test purposes.
- Provides transmit system side FIFO interface with invalid cell detection.
- Performs rate adaptation through the insertion of configurable IDLE cells.
- Provides line side End of Cell (EOC) signaling with generated idle cell indications.
- Performs delineation on incoming ATM cells and provides status signals for Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD) state conditions.
- Supports configurable delineator OCD and LCD count capability.
- Detects and optionally drops incoming IDLE cells.
- Supports HEC (COSET addition available through input signal conditioning) correction and detection modes of operation.
- Provides status signaling for corrected and uncorrected cells.
- Provides receive system side FIFO interface with Start of Cell (SOC) and End of Cell (EOC) signaling.
- Traffic Manager
- Digital cross connects
- SONET/SDH line cards
- Test equipment