MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
NAND Flash Controller
• Support for 8-bit NAND-Flash chips
• Reading speed up to 40 MB/sec
• Hardware checksum calculation
• Asynchronous DMA-Master interface allows CPU context switch during transaction, reducing CPU load
• Bulk read operations are supported to reduce number of interrupts
• Interfaces:
8-bit parallel NAND-Flash interface
32-bit AMBA AXI Master
APB Slave for configuration
Linux MTD drivers are available
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