The Nand Flash controller is fully configurable (page size, timings, ...). The design support and integration is directly taken in charge by the Ip-Maker designers.
The Nand Flash controller is fully compliant with the last memory specification (ONFI 3.0) allowing application to reach rate up to 400Mbits/s. The large configuration capabilities allow user to fit its application. Your design will include the last memory technology with all its benefits.
- Fully compliant to ONFI 4.0 standard.
- Supports NAND Flash memories from Micron, Samsung, Toshiba, and others.
- Supports all ONFI commands (mandatory and optionnal).
- Full access to spare aera.
- Supports SLC and MLC Nand Flash devices.
- Page size : 512B, 2kB, 4kB,8kB and 16kB.
- Programmable timings.
- ECC: BCH with the capability to correct up to 76 error bits per unitary block (256, or 512 or 1024 bytes)
- Data interface
- Bandwidth up to 800 MB/s (ONFI DDR3 mode).
- Supports all mode.
- 8/16 bits interface.
- Supports independent data bus for command, read and write path, that allows full duplex runs.
- System interface
- RAM like native and AXI full or Avalon
- Supported simulators
- MTI Modelsim-Verilog.
- Cadence NC-Verilog.
- One interface for up to 2 channels
- One common interface is used to manage all data flow of all implemented channels.
- Internal or external DMA
- Thank to the generic parameters, internal DMA can be implemented.
- So user can choose between using external DMA or using internal DMA.
- Management with outstanding requests (up to8 per channel)
- Increase significally the flexibility of data management.
- Increase the throughput because the next transfer order is already loaded
- RTL design in verilog.
- Simulation testbench.
- Synthesis scripts for Xilinx, Altera and Design Compiler.
Block Diagram of the Nand Flash controller IP Core