NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize a Time of Day sink via NMEA over UART. The whole message creation, algorithms and calculations are implemented in the core, no CPU is required. This allows running NMEA synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface. This core only uses the second part of the clock, frequency and sub-second offset distribution shall be done in a combination with the PPS Master Clock.
All calculations and corrections are implemented completely in HW.