The Capless LDO IP core is optimized for Application Specific Integrated Circuits (ASICs), System-on-a-Chip (SOC) and microprocessor integration. The Capless LDO can hold a steady output voltage reference without using an external capacitor. The LDO uses Noise Quencher(TM) Technology to provide unparalleled power supply rejection at high frequencies.
- Input Power Supply: 2.3 V to 3.6 V
- Output Voltage: 0.8 to 3.3 V (programmable)
- Maximum Load Current: 300 mA
- Contact Vendor for Product Brief
- Adds value to your microchip with embedded power management
- Fewer components and smaller board area (NO external capacitor)
- Improved reliability
- Reduced inventory and reduced BOM management overhead
- Longer battery life (save power through integration)
- Low risk for customer product/program with a silicon proven capless LDO IP core.
- Spice Netlist and/or Cadence Schematic
- IP Datasheet, User’s Guide, and Test Plan
- Behavioral Model