AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
MIPI CSI-2 Controller Core
It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-8 D-PHY data lanes (8 bit PPI) and 1-4 CPHY lanes (16 bit PPI). The 32 bit core width can support 1-4 D -PHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI) The core implements all three layers defined by the CSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the CSI-2 standard. Separate Transmit (Tx) and Receive (Rx) versions of the core are available.
The core’s Local Interface is an easy to use pixel based interface (single, double, quad, octal pixel wide). An optional Hsync/Vsync Video Interface wrapper is also available. The core is delivered fully integrated and verified with the user’s target D/C-PHY. Contact Rambus for a complete list of supported PHYs.
The core is also provided with the CSI-2 Testbench which provides a CSI-2 Bus Functional Model.
Rambus offers a CSI-2 Demonstration System which includes an FPGA Board, MIPI Interface Card and MIPI Camera. Contact Rambus for more information.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
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MIPI CSI-2 Controller IP
- MIPI CSI-2 Receiver v 1.3
- MIPI CSI-2 Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI CSI-2 Transmitter v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Transmitter v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY