Northwest Logic’s DDR4 Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR4 SDRAM devices. The core also performs all initialization, re-fresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core supports all new DDR4 SDRAM features, including: 3DS device configurations, write CRC, data bus inversion (DBI), fine granularity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY. Northwest Logic supports a broad range of third party and its own soft DDR PHY. Contact Northwest Logic for more info.
Northwest Logic also provides IP Core customization services. Contact Northwest Logic for a quote.
- Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
- Minimal latency achieved via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports half-rate and quarter-rate clock operation
- Supports DDR4 SDRAM 3DS device configurations
- Multi-mode controller support
- Full run-time configurable timing parameters and memory settings
- DFI Compatible
- Full set of Add-On Cores available
- Delivered fully integrated and verified with target DDR PHY
- RDIMM and LRDIMM support
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and integration services available
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates