The IntelliProp NVMe Bridge utilizes the IntelliProp NVMe Host Accelerator Core and the IntelliProp NVMe Target Core to create an NVMe protocol bridge. The bridge is architected such that the command submissions, completion notifications and data transmissions may be either passed through without interruption or intercepted for analysis or modification. The architecture implements a ”sandbox” area in the bridge so that IntelliProp customers may implement their own custom RTL and/or firmware in the bridge.
The protocol interface is compliant to the NVMe 1.3 specification and is fully verified using a coverage driven methodology in pseudo random simulation.
The IntelliProp NVMe Bridge, IPC-NV171-BR, implements a protocol bridge by receiving and parsing commands via the IntelliProp NVMe Target Core and forwarding them to the IntelliProp NVMe Host Accelerator Core for delivery to the NVMe SSD Endpoint. Customizable bridging logic between these two cores facilitates command management, including forwarding and tracking outstanding commands and routing data accesses appropriately, while a Sandbox area provides visibility and flexibility into the buffered data as it is transferred between the Host and the Target. Registers in the bridging logic provide firmware with a mechanism to control data movement, to manually issue individual commands, and to control status and behavior of the bridging function. A processor or other management agent is expected to receive and properly complete administrative commands from the NVMe Target Core, while I/O commands are executed autonomously by the bridging logic. As a result, the NVMe Bridge provides transparency between the Host and the Endpoint SSD, while offering the designer flexibility in command and data manipulation.
- Fully compliant to the NVM Express 3 industry specification
- Automated initialization process with PCIe Hard Block
- Automated command submission and completion
- Scalable I/O queue depth
- Support for 256 outstanding I/O commands
- Processor or State Machine driven interface
- Submission queue command context error prevention
- Support for block sizes from 512 byte to 16kB
- Application layer (command based) interface with Processor interface
- High performance read/write caching
- Data Deduplication
- LBA Remapping
- Namespace manipulation
- Data encryption
- Data compression
- Endpoint aggregation