OCTAL SPI Master IP

Features

• Implemented in Unencrypted Verilog, VHDL and SystemC
• Compliant with ONFi 2.3/3.0/4.0 specifications.
• Supports Source Synchronous and Asynchronous data interfaces.
• Supports all mandatory and optional commands.
• Supports 16 bit bus width operations.
• Supports Read ID commands.
• Supports Synchronous reset commands.
• Interleaved commands support.
• Multiple LUN Operation support.
• Multi-plane commands support.
• Reset LUN command support.
• Configurable timing modes for Source Synchronous and Asynchronous data interface.
• Supports Partial Page programming and copyback programming.
• Source Synchronous data interface supports Clock Stop feature.
• Supports dual data bus.
• Supports Small Data Move command for both Program and Copyback operations.
• Ability to generate Vendor Specific Commands and Block Abstracted NAND Commands.
• Rich set of configuration parameters to control ONFi functionality.
• Supports constrained randomization of protocol attributes.
• On-the-fly protocol and data checking.
• Supports DDR data interface.
• Supports Volume select commands.
• Detects and reports the following errors.
• -> Page address error
• -> CRC error
• -> Command not support error
• -> Illegal command error
• -> Synchronous reset error
• -> Read ID error
• -> Reset LUN error
• -> Read cache error
• -> Read UID error
• -> Lun address change error
• -> Copyback program error
• -> Change row address error
• -> Read status enhanced error
• -> Interleave page address error
• Status counters for various events on bus.
• ONFI Verification IP comes with complete testsuite to test every feature of ONFI specification.
• Fully synthesizable
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The OCTAL SPI MASTER interface is available in Source and netlist products.
• The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and linux driver package
• Documentation contains User's Guide and Release notes.

• see the entire OCTAL SPI Master IP datasheet
• get in contact with OCTAL SPI Master IP Supplier