Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
One Port Register File Compiler IP, UMC 28nm HLP process
View One Port Register File Compiler IP, UMC 28nm HLP process full description to...
- see the entire One Port Register File Compiler IP, UMC 28nm HLP process datasheet
- get in contact with One Port Register File Compiler IP, UMC 28nm HLP process Supplier