One Port Register File Compiler IP, UMC 40nm LP process

UMC 40nm LP Logic process Single Port Register File memory compiler with LVT peripheral.

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Memory

DDR4/DDR3 Memory Controller
LPDDR2/LPDDR1 Memory Controller
LPDDR2/DDR3 Memory Controller
LPDDR3/LPDDR2 Memory Controller
LPDDR3/LPDDR2/DDR3 Memory Controller
HBM Subsystem IP Gen2

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