One Port Register File Compiler IP, UMC 55nm eFlash process

UMC 55nm eFlash with peripheral HVT One Port Register File.

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Memory IP

HBM2/2E PHY
High Performance DDR4/3 Memory Controller
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
Memory (SRAM, DDR, NVM) encryption solution
Anti Row-Hammer / Memory Attacks
Hyperbus Flash Memory Controller

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