One Port Register File Compiler IP, UMC 55nm eFlash process

UMC 55nm eFlash One Port Register File with Power Gating.

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Memory IP

The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
HBM Subsystem IP Gen2
High Performance DDR4/3 Memory Controller
xSPI Flash Memory Controller
HBM2/2E PHY
Hyperbus Flash Memory Controller

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