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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY
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Block Diagram of the ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI 4.1 PHY IP IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 12nm 12FFC,FFC+
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 16nm 16FFC,FF