ONFI 5.0 Controller
The IP consists of two primary components: a host controller and two or more high speed PHY interface controllers. The host controller is controlled via an AXI slave port. A scatter/gather DMA provides a separate AXI master port, allowing for extended unattended reads or writes. The host controller supports either AXI3 or AXI4, and a user configurable data path width.
View ONFI 5.0 Controller full description to...
- see the entire ONFI 5.0 Controller datasheet
- get in contact with ONFI 5.0 Controller Supplier
Block Diagram of the ONFI 5.0 Controller IP Core

ONFI 5.0 IP
- ONFI 5.0 PHY
- Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 5nm 5FF
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 6nm 6FF
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 12nm 12FFC,FFC+
- Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 0.13um LV,LVOD