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ONFI IO Pad Set
The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI 3.0 signaling. This library also meets the requirements for Toggle 2.0 signaling. The pad set includes a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated ONFI domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
ONFI 3.0 Single-Ended Driver /Receiver
ONFI 3.0 Differential Clock Driver / Receiver
ODT / ZO Calibration Cell
Voltage Reference
The ONFI I/O library supports all impedance modes defined in the ONFI 3.0 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).
ONFI 3.0 Single-Ended Driver /Receiver
ONFI 3.0 Differential Clock Driver / Receiver
ODT / ZO Calibration Cell
Voltage Reference
The ONFI I/O library supports all impedance modes defined in the ONFI 3.0 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).
Features
- ONFI Single-Ended Driver / Receiver Features:
- Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30Ω / 50Ω / 75Ω / 100Ω / 150Ω
- o ZOUT = 18Ω / 25Ω / 35Ω / 50Ω
- o Off state – Z / pull-up / pull-down / bus keeper
- Receiver – single-ended and pseudo-differential outputs
- Powered by 1.8V / 3.3V I/O and 1.1V / 1.2V core supplies
- Maximum operating frequency – 200 MHz
- Differential Clock Driver / Receiver Features:
- Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30Ω / 50Ω / 75Ω / 100Ω / 150Ω
- o ZOUT = 18Ω / 25Ω / 35Ω / 50Ω
- o Off state – Z / pull-up / pull-down / bus keeper
- Receiver – single-ended and true differential outputs
- Powered by 1.8V / 3.3V I/O and 1.1V / 1.2V core supplies
- Maximum operating frequency – 200 MHz
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
View ONFI IO Pad Set full description to...
- see the entire ONFI IO Pad Set datasheet
- get in contact with ONFI IO Pad Set Supplier
IO
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- LDO Capless Fast Response Series ( Vin = 1.65-1-95V; Vo = 0-75-1.0V; Io = 150 mA ) - TSMC 28nm
- High voltage analog IO pads
- Low Leakage Analog IO Pads