NAND Flash Interface controller that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design pre-association. The solution also provides the means for a system to seamlessly make use of new NAND devices that may not have existed at the time that the system was designed.
Support for High Speed NAND Flash memories (up to 400 MT/s)
Synchronous I/O Operations (DDR and DDR2)
Asynchronous I/O Operation (SDR)
Command set: ONFI NAND Flash Protocol
Data Strobe signal provides a hardware method for synchronizing data in the synchronous interface
DMA Support for faster data transfer
Supports 4 bit Error Correction per 512 bytes