English
14-bit, 4.32Gsps Ultra high speed Wideband, Time-Interleaved Pipeline ADC IP
You are here:
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
View ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process full description to...
- see the entire ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process datasheet
- get in contact with ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process Supplier
Interface Solution IP
- AXI Interface Core
- PCIe 5.0 Controller with AMBA AXI interface
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.0 Controller supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with native user interface
- Many-Channel Centralized DMA Controller with AMBA AXI Interface
- CCIX 1.1 Controller with AMBA AXI interface