English
You are here:
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
View ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process full description to...
- see the entire ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process datasheet
- get in contact with ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process Supplier
Interface Solution IP
- Northwest Logic AXI Interface Core from Rambus
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Controller IP for PCIe 1.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Common Public Radio Interface (CPRI) v.7.0 IPC
- D2D Controller IP (Die-to-Die Interface)