The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB v4.6) Bridge module translates OPB transactions into PLBV46 transactions. It functions as a slave on the OPB side and a master on the PLBV46 side. The OPB to PLBV46 Bridge is necessary in systems where an OPB master device, such as a DMA engine or an OPB based coprocessor, requires access to high performance system resources on the PLBv46 bus. The Xilinx OPB to PLBV46 Bridge design allows customers to tailor the bridge to suit their application by setting certain parameters to enable and disable features.
- Bridge Functions
- Uses 16-word deep posted write buffer to decouple OPB and PLBV46 transactions.
- Uses 16-word deep read prefetch buffer to eliminate bridge related system lockup issues.
- PLBV46 Master interface
- 32-bit native device width
- Communicates with 32-, 64-, and 128-bit PLBV46 slaves
- Non-burst transfers of 1 to 4 bytes
- Uses fixed length, burst signaling of up to 16, 32-bit words.