The open source Viterbi decoder with AXI4-Stream interface is capable of decoding most of the convolutional codes as defined by various standards.
- Design-time configuration of encoder polynomials (different number of states and different code rates).
- Support for recursive and non-recursive convolutional codes.
- Windowing technique for reduced latency and memory requirements (with acquisition).
- Design-time configuration of quantization, maximum window size, RAM usage (distributed RAM vs. Block RAM).
- Run-time configuration of block length.
- Run-time configuration of window length and acquisition length.
- Block-to-block on-the-fly configuration.
- Configurable for most standards that apply convolutional codes (GSM, UMTS, CDMA, CDMA2000, WiMAX, WiFi, DVB, ...).
- Pipelined design for high payload throughputs (about 1 bit per clock cycle).
- AXI4-Stream interface for simple integration.
- Up to 250 MHz on Xilinx Virtex-6 FPGA (Speedgrade 1).
- VHDL source code available under GPL license.
- Commercial support and licenses available.
- VHDL source code, VHDL testbench, documentation.