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OSU processor, optimized for 10GE services over OTU2/OTU2e/OTU1e lines
The TPS3202MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3202MP processors accept 2x 10GE client signals, process and present them to either OSU or ODU containers for their transport over OTU2 bearers. TPS3202MP processors support OTU, ODU and OSU signal overheads. For Ethernet client-services, Ethernet bandwidth limiting is provided, along with integrated IEEE 1588 V2 H/W Time Stamping. TPS3202MP processors support hitless bandwidth adjustment of OSU containers carrying Ethernet information. Integrated HDLC controllers can be assigned to GCC in-band communications channels. TPS3202MP processors are offered as complete turn-key solutions, including built-in jitter filters, without necessitating external PLLs. TPS3202TP processors present OSU or ODU containers for their transport over OTU2/OTU2e/OTU1e bearers.
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Block Diagram of the OSU processor, optimized for 10GE services over OTU2/OTU2e/OTU1e lines
OSU processor IP
- OSU processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines
- OSU processor, optimized for E1/T1/T3/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines
- OSU processor, optimized for STM1/OC3/STM4/OC12/FE/GE services over OTU2 lines
- OSU processor, optimized for E1/T1/T3/STM1/OC3/STM4/OC12/FE/GE services over OTU2 lines