The Xelic Optical Transport Network (OTN) ODUCn Multiplexer Core (XCOCnFMX) performs mapping of incoming ODUk slice signals into ODUCn frame structures using generic mapping procedure (GMP) justification methods. Likewise, incoming line side ODUCn frame structures are demapped to system side ODUk slice signals while providing timing through an external GMP extract port. A flexible data bus architecture is used for ODUk and ODUCn transport to provide n x 256-bit transfers (where n is equal to the number of 20x5G tributary slots) for FPGA applications and ASIC implementations. The core is parameterized to allow for ODUCn rates of ODUC1, ODUC2, ODUC3, ODUC4, etc. In a typical configuration using a parameter n value of 4, the core will support either a single ODUC4, 4xODUC1, 2xODUC2, or 1xODUC3 + 1xODUC1.
The XCOCnFMX Transmit Processor inserts OPUCn overhead including OMFI, MSI, and generic mapping procedure (GMP) justifications. OPUCn reserved overhead field information is blanked. Diagnostics support includes optional corruption of inserted CRC-6 and CRC-9 fields. Transport overhead frame and multi-frame insertion is provided but all other transport level overhead is blanked. Multiplexer configuration is achieved through the programming of internal register. Traffic can be reprovisioned at any time for selected timeslots while other timeslots remain undisturbed. Bypass mode is supported for any ODUCn rate signal.
The XCOCnFMX Receive Processor interprets incoming OPUCn overhead including OMFI, MSI, and generic mapping procedure (GMP) justifications. Incoming error detection is reported through internal interrupts. Incoming error detection includes incoming FAS and MFAS sequence errors, TSF detection, GMP errors, CRC-6 and CRC-9 errors, OMFI sequence errors, MSI mismatch value detetection, etc. CRC-6 and CRC-9 correction is enabled through register control. Automatic Server Signal Fail (SSF) generation is provided for various errors detected and can be forced directly through register control. An external GMP port is provided to optionally (register controlled) generate timing for receive client side timesliced data when an SSF condition is detected.
The XCOCnFMX provides line facility and line terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 32-bit generic register interface for access and configuration of internal memory mapped locations is included.