The Xelic Optical Transport Network (OTN) ODTU01 Multiplexer Core (XCO01MX) performs tributary timeslot interleaving of two independent ODU0 data streams and maps them into an ODU1 or OTU1 frame structure. OPU1 multiplex overhead is inserted and automatic justification control is provided based on programmable FIFO thresholds or incoming PJ/NJ request signaling. Incoming line side OPU1 overhead is interpreted with error and justification detection reported. System side ODU0 frames are transferred using two separate 8-bit data bus ports operating at a clock rate up to 166.63MHz. Line side data is transferred at an OTU1 rate using a 16-bit data bus operating at 166.63MHz or at an ODU1 rate using a 16-bit data bus operating at 156.17MHz.
The XCO01MX Transmit Processor contains two FIFOs with upper threshold, lower threshold, and overflow/underflow detection. Justifications (positive and negative) for each ODU0 data stream are performed through a transmit OPU processor. OPU1 overhead insertion includes Payload Structure Identifier (PSI), justification overhead and reserved fields. PSI field insertion consists of payload type, multiplex structure identifier, and reserved bytes multi-frame information. A test mode is available to insert PRBS data into any of the 2 ODU0 frame timeslots. ODU0 frames are mapped into either ODU1 frames or OTU1 frames with blanked FEC. Generated ODU1/OTU1 frames contain blanked OTU1 and ODU1 overhead. FAS and MFAS information is inserted into outgoing frames in addition to OPU1 overhead.
The XCO01MX Receive Processor contains a frame position counter synchronized to incoming FAS and MFAS frame indicators. OPU1 overhead is extracted from incoming frames and interpreted with various error conditions reported to an internal maskable interrupt register. Positive and negative justifications are detected and reported though output signaling and internal interrupts. Tributary timeslot de-interleaving is performed on incoming frames and ODU0 frames are de-mapped and delivered to two internal FIFO structures. Configurable depth FIFOs are implemented for each system side ODU0 signal interface.
Performance counters (configurable for interval count capture) are provided for the accumulation of inserted (XCO01MX transmit processor) and detected (XCO01MX receive processor) positive and negative justification events. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO01MX provides Transmit Processor terminal loopback and Receive Processor facility loopback modes of operation for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.